mattandClaude Opus 5
d2e4c974dd
ESP-IDF v5.3.2 firmware for the CrowPanel 2.1" rotary display. Builds clean;
nothing has been run on hardware yet.
Hardware verified against Elecrow's own source for this board and
cross-checked against their ESPHome config, per PRD 8.1. Three corrections to
the PRD's pinout, all documented in docs/HARDWARE.md:
- touch is CST826 at 0x15, not CST816 (chip ID reads 0x11, not 0xB4)
- the ST7701S needs a 3-wire SPI bus on GPIO 16/2/1 that the PRD omitted;
without it the init sequence cannot be sent and the panel stays black
- the backlight is GPIO6
Two further departures from the PRD, both forced by facts on the ground:
- Transport is MQTT, not HTTP. zigbee2mqtt has no REST endpoint for live
sensor state. Subscribing to the broker also gets retained topics, so
every room's last reading arrives on connect rather than after a poll.
- The furnace is 2-wire R/W with no C, not 3-wire. The board needs its own
5V supply. The thermostat's 5 CPH setting is enforced as a minimum
12-minute period between heat-call starts, which a minimum off-time alone
does not achieve.
All of PRD section 5 is implemented in the relay layer itself: fail-open,
watchdog-gated output, max on-time, min off-time, cycle-rate limit, startup
lockout, and the stale-data fallback ladder down to open-loop freeze
protection. The one gap that cannot be closed in software — the PCF8574 not
resetting when the ESP32 does — is documented rather than papered over.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
56 lines
1.8 KiB
C
56 lines
1.8 KiB
C
/*
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* ST7701S + RGB panel, 480x480 round.
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*
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* Two things about the configuration here are deliberate and load-bearing:
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*
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* No bounce buffers. The bounce-buffer refill ISR reads PSRAM, which shares
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* the cache with flash on the S3, so any NVS write while the panel runs faults
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* with "Cache disabled but cached memory region accessed" (PRD 8.2). This
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* project writes settings to NVS at runtime, so instead of pausing the panel
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* around every write we simply do not use bounce buffers: the LCD DMA reads
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* the framebuffer out of PSRAM directly and never touches the cache.
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*
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* Two framebuffers. Writing into the framebuffer currently being scanned
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* races the LCD's reads, and the corruption persists because LVGL does not
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* know those pixels are wrong and never reinvalidates them (PRD 8.2). With
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* num_fbs=2 the panel driver swaps whole buffers instead.
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*
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* 480x480x2 bytes x 2 buffers is ~920KB of the 8MB PSRAM.
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*/
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#pragma once
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#include <stdbool.h>
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#include <stdint.h>
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#include "esp_err.h"
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#include "esp_lcd_panel_ops.h"
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#define DISPLAY_H_RES 480
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#define DISPLAY_V_RES 480
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/*
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* Bring up the panel: expander power/reset sequencing, 3-wire SPI init,
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* RGB bus, backlight.
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*
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* Requires i2c_bus_init() and pcf8574_init() to have run. PRD 8.2 also wants
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* WiFi up before this point.
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*/
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esp_err_t display_init(void);
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/* The esp_lcd panel handle, for the LVGL port. */
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esp_lcd_panel_handle_t display_panel(void);
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/* Both framebuffers, for LVGL to render into directly. */
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esp_err_t display_get_framebuffers(void **fb0, void **fb1);
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/* Backlight, 0-100. */
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void display_set_backlight(uint8_t percent);
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/*
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* Fill the screen with vertical colour bars, bypassing LVGL.
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*
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* This is the PRD phase-2 check: it proves the init sequence, the RGB bus and
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* the timings independently of anything LVGL does.
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*/
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void display_test_pattern(void);
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